A pipelined microprocessor for logic programming languages
نویسندگان
چکیده
In the Japanese Fifth Generation Computer Systems Project, a large scale parallel inference machine, PIM/m, is being developed. In PIM/m, up to 256 processor elements are connected to form a two-dimensional mesh network. The processor element has a pipelined microprocessor specialized to the execution of logic programming languages. The microprocessor, called PU (Processing Unit), is also used as a key component of AI workstations. Thus, PU has capability to execute two di erent type logic programming languages, KL1 for PIM/mand ESP for the AI workstation. For e cient implementation of both languages, data typing and dereference are very important. For these operations, PU has powerful mechanisms to manipulate tagged data. Especially, the pipelined data typing and dereference are the most unique features of PU. Those mechanisms greatly contribute to the high performance, 833 KLIPS for KL1 append, and 1282 KLIPS for ESP.
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